IC Package Layout Design

Job Location : Bengaluru

Exp : 6 to 13 years

Notice Period : Immediate to 30 Days Only

Qualification : BE / BTech / ME / MTech / MS - Electricals & Electronics Engineering

Roles & Responsibilities :

• IC Package Layout Design Engineer
• Experience with IC Package Layout Design using Cadence Allegro APD (will consider Mentor Graphics XPD, XSI tools experience also)
• Good understanding of package / substrate design and package assembly rules related to flip chip designs.
• Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantage.
• Expertise in High-Speed Complex PCB and Package designs with HDI, Blind and Buried Via technologies.
• Hands-on expertise with PCB and Package layout designs involving High Speed Parallel Bus interfaces including DDR, GDDR and HSIO interfaces including PCIe, SERDES and Type C.
• Good Exposure to Stackup design, substrate DFM, DFA rules and adherence.
• Should have expertise in constraint setting in layout tool.