SOC RTL / DFX execution Lead (SMTS Silicon Design Engineer)

EXPERIENCE & QUALIFICATIONS :

• BS / MS / PhD in EE / ECE / CE / CS with at least 10+ years of industry experience in SOC RTL / DFX execution with added exposure to high speed PHY or Serdes IPs design.
• Experience with the development of a complete TestChip RTL (including integration of IEEE1149.1 TAP, GPIOs etc) from early RTL design to post-silicon support.
• Exposure to MCM (multi-die integration into a package) would be desirable.
• Integration of several IPs (with or without integrated JTAG controllers) into the testchip environment.
• Experience with integration of PLLs and DFX care-abouts thereby.
• Test chip SOC level ICL / PDL transition and implementation.
• Understanding of STA fundamentals, experience with SDC development.
• Experience with UPF development.
• Experience with ATPG patterns translation from IP level to SOC level.
• Familiarity with SystemVerilog and UVM.
• Strong problem solving and debug skills across various levels of design hierarchies

Skills Required

Physical Design, Dft, Jtag, Asic, RTL, Soc