Proficiency in Verilog / VHDL for FPGA design and test logic implementation.
Hands-on experience with DFT tools (Synopsys DFT Compiler, Tessent, Mentor Tessent, Cadence Modus, or similar).
Strong knowledge of JTAG (IEEE 1149.1, 1149.6) , scan insertion, #ATPG, #MBIST, LBIST, and fault modeling.
Experience in # timing analysis and synthesis-aware DFT implementation .
Familiarity with FPGA prototyping and board bring-up .
Hands-on scripting skills in # Python, TCL, Perl, or Shell for DFT automation.
Preferred Qualifications :
Experience in AI / ML-driven DFT automation .
Knowledge of high-speed interfaces and SERDES testing .
Experience with post-silicon validation and ATE (Automated Test Equipment) .
Strong debugging skills using logic analyzers, oscilloscopes, and FPGA tools .
Why Join Us?
Work on cutting-edge FPGA-based designs for high-performance computing, automotive, or AI applications .
Opportunity to architect and implement industry-leading DFT methodologies .
Be part of a highly skilled team pushing the boundaries of FPGA design & test innovations .
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Senior Dft Engineer • Hyderabad, Telangana, India
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