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Member of Technical Staff - HBM SOC Physical Design Engineer
Micronbangalore, India30+ days ago
Job descriptionIn-depth technical expertise in one or more areas : Physical Synthesis, Floor-Planning, Place and Route, Power Grid, Clock Tree Synthesis, Static Timing Analysis for Partition Level and Full Chip Level Timing Closure, SRAM Compilers, Physical Design Verification (DRC / LVS), Formal Equivalence Verification (FEV), ATPG. Proficiency in writing TCL with demonstrated experience in using TCL with one or more Physical Design Tools. A solid understanding of Unified Power Format (UPF) for describing power intent. Excellent knowledge of Synthesis Design Constraints and Static Timing Analysis. Excellent understanding of clocking concepts, including asynchronous crossings and structures used to synchronize clock domain crossings. Good understanding of computer architecture concepts, including SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc. 10+ years of relevant job / skill-related experience. Experience delivering highly technical solutions. BSEE or higher. Familiarity with DRAM operation and JEDEC specifications, preferably with the HBM product family. Knowledge of scripting languages such as Python. Experience in any of the following focus areas : memory array architectures, on-die and off-die high-speed signaling, PHY & interface development, power delivery network planning and optimization, power consumption reduction, CMOS requirements identification, packaging technologies, and thermal modeling. Good verbal and written communication skills with the ability to efficiently synthesize and convey sophisticated technical concepts to other partners and leadership. A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds. An innovative approach that is open to improving any of our processes or products. Bengaluru, India
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
What’s Encouraged Daily :
- Completing various tasks in the netlist to GDSII implementation for partition(s), meeting schedule, and design goals.
- Collaborating with the Architect, Front End Design, and CAD teams to deliver best-in-class designs.
- Assisting Front End Design and Integration Engineers with SRAM / RF specification and synthesis design constraints.
- Resolving and improving design and flow issues related to physical design, identifying potential solutions, and working with CAD teams as needed.
- Being proactive in identifying and flagging quality issues, performance problems, and opportunities to reduce power consumption, whether in Architecture, Microarchitecture, RTL, or Circuits.
- Debugging and identifying root causes and solutions for netlist timing issues or post-silicon timing issues.
How To Qualify :
What Sets You Apart :
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Member Of Technical Staff • bangalore, India
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