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Sr. / Lead Design Verification [Urgent]

Sr. / Lead Design Verification [Urgent]

ACL DigitalIndia
21 hours ago
Job description

Experience : 4 to 12 Years.

Location : Bangalore.

  • Must have hands-on experience coding in System Verilog / UVM.
  • Experience developing testbenches for block level or IP level verification.
  • Experience working on subsystem or SoC level would be helpful.
  • Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules.
  • Developing and maintaining block level test benches.
  • Vplan, regression and coverage closure.
  • Work on testbenches with real number modeling.
  • Netlist and Gate level simulations.

Notice Period : 30 to 90 days

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Design Verification Lead • India

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