STA engineer (full chip)

Quest Global is an organization at the forefront of innovation and one of the world’s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills :

Roles & Responsibilities :

• Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)
• Strong experience in Static Timing Analysis (PrimeTime – SI), EM / IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).

Required Skills (Technical Competency) :

6+ years of exp in Hands on Chip top and Block level Timing closure.

Desired Skills :