Sr Principal Solutions Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The role will involve :

• Writing designs using Verilog / System Verilog / C / C++ / TCL for functional and performance testing of overall Protium flow.
• Performance and functional validation of multiple features on Protium.
• Hands on debug and the ability to converge on feature delivery.
• Provide feedback to the development team and work with the team for new feature development.

Key requirements :

1. (EE) – must have a very good understanding of Digital Logic Systems / Timing Analysis etc.

2. Hands-on knowledge of Verilog and System Verilog is a must.

3. Must have good analytical and problem solving skills .

4. Should be able to create test plans and execute those effectively.

5. Must be hands on with either simulation or hardware emulation or FPGA prototyping.

A minimum experience of 10+years is required.

We have a mission to help solve technologies' toughest challenges in order to make a lasting, positive impact on our world!

We’re doing work that matters. Help us solve what others can’t.