UFS Application Engineer, Staff

What You ll Need :

• Bachelor s degree or Master s with with 5+ years of relevant experience in ASIC design.
• Proficiency in Verilog HDL, synthesis, simulation, and verification.
• Knowledge of MIPI UFS / UniPro protocols and high-speed SERDES or parallel interfaces is a plus.
• Experience with Synopsys tool suites is advantageous.
• Strong verbal and written communication skills in English.

Skills Required

SERDES, Verilog Hdl, Synthesis, ASIC Design, Communication Skills