Senior System IP Design Engineer

We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V / ARM-based SoCs. This role is hybrid, based out of Bangalore, India. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

8–12 years of experience in ASIC design, with expertise in microarchitecture and RTL for complex subsystems

Skilled in Verilog / SystemVerilog and comfortable working across design, debug, and analysis

Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes

Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI)

Awareness of functional safety (ISO 26262) practices in hardware design

What We Need

Ability to own microarchitecture definition and RTL development of power management subsystems

Experience driving verification closure, performance debug, synthesis, timing, and power optimization

Strong skills in LINT, CDC / RDC, and power intent checks

Proficiency with DV and analysis tools like Verdi, NCSIM, and power estimation tools

Hands-on experience in design-for-power, debug, and test methodologies

What You Will Learn

Building power-efficient, high-performance subsystems for advanced RISC-V / ARM architectures

Cross-functional collaboration from concept to silicon bring-up

Enhancing subsystem performance through innovative power, performance, and area optimizations

Leadership and mentorship experience by guiding junior design engineers