DV Engineer

SoC / SS Lead Engineers : Experience in development of UVM based verification environments from scratch. Experience with Design verification of ta-center applications like Video, AI / ML and Networking designs. Experience in Mercurial (Hg), Git or SVN. Experience with low power design. Experience working across and building relationships with cross-functional design, model, and emulation teams.Strong in Funmentals, Digitial Concepts, Debugging

Low Power and GLS Simulations will be plus