FPGA / RTL Engineer

The requirement is immediate so please only apply if you can join immediately or in about 1 month.Please fill this form to take things forward : Developer Requirements : 1) Should be comfortable with Vivado2) Coding language : VHDL / Verilog / SystemVerilog3) Should have developed AXI peripherals for Zynq and other Xilinx FPGAs. Should have a knowledge of the PS and PL parts.4) Should know how to implement timing and other constraints5) Should know how to interface external memory using the EMC in Vivado6) Should know how to write test benches and run simulations7) Should have a working knowledge of Matlab, C & Python8) Should know how to configure Microblaze and run bare metal C code9) Should know how to write PC side code for interfacing over RS23210) Should know how to read schematics11) Should have implemented State Machines