Risc-V Cpu Core Testbench Lead

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

RISC-V CPU Core Testbench Lead

Responsibilities

Design, develop, and maintain highly configurable testbench environments for RISC-V cores and clusters using synthesizable SystemVerilog, UVM and C++.

Build key testbench components including harnesses, transactors, functional models, checkers and utilities such as preloaders, trickbox etc.

Contribute to the CVM (C++ Verification Methodology) - a UVM-inspired framework - by applying modern C++ features to simplify testbench development and improve maintainability.

Enable integration of UVM-based block-level environments into the broader testbench framework to support hybrid simulation workflows.

Ensure testbench portability across simulators (including open-source Verilator) and commercial emulation platforms.

Support architecture and microarchitecture bring-up for both core and cluster DV teams by enabling rapid validation of new features.

Develop debugging tools and automation to accelerate root-cause analysis for failures across simulation and emulation.

Collaborate closely with RTL, DV, and tooling teams to define reusable infrastructure and scalable test strategies.

Experience and Qualifications

Bachelor’s or Master’s degree in Electronics, Computer Engineering, or a related field, with 9+ years of relevant industry experience.

Strong proficiency in modern C++ and SystemVerilog, including familiarity with verification libraries or testbench infrastructure.

Hands-on experience with SystemVerilog UVM, including environment construction and integration into larger simulation contexts.

Experience working with or contributing to custom DV methodologies (e.G., UVM, custom C++-based frameworks).

Solid understanding of software engineering principles such as design patterns (e.G., publish-subscribe), multithreaded programming, and coroutines.

Working knowledge of CPU architectures (RISC-V, ARM, or x86) and microarchitectural design elements such as pipelines, caches, MMUs etc.

Strong debugging and analytical skills across layers of abstraction — from software and compiler traces to assembly programs and RTL waveforms.

Excellent communication and collaboration skills, with a track record of working effectively in fast-paced team environments.

Self-driven and adaptable, with a bias for automation, reuse, and scalable infrastructure.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.