System Cache Verification Engineer

We are seeking experienced Design Verification Engineers with 3+ years of experience, specifically in IP and subsystem verification, to join our highly talented verification team at Mediatek Bangalore. The candidate needs to have a strong background in computer architecture, with some experience in verifying caches, TLB’s , load-store units, on-die memories or coherency verification. Should have experience in verification methodologies, test planning & testbench design and coverage closure. Must have strong System Verilog programming skills and experience with UVM methodology. Experience with OOPs programming is a plus. Should possess excellent problem-solving skills and ability to work collaboratively in a fast-paced environment spanning across geographies.

Senior candidates with experience in leading teams will be considered for higher roles.

Key Responsibilities :

Develop and implement comprehensive verification test plans for IP blocks and subsystems.

Create and / or enhance testbenches, test cases, and verification flows using System verilog and UVM methodology.

Drive functional verification of RTL designs at IP level and Sub System level, including simulation, debugging and coverage closure, ensuring high-quality and robust designs.

Collaborate with design engineers to understand detailed design specifications and target corner cases IP and subsystem levels.

Generate and analyze verification metrics to regularly track progress and ensure timely coverage closure.

Participate in design and verification reviews, providing technical expertise and insights.

Incorporate newer verification techniques and methodologies to improve verification efficiency and effectiveness.

Mentor junior verification engineers and provide technical guidance.

Qualifications & Experience :

Bachelor's or Master's degree in Electrical / Electronics Engineering, Computer Engineering, or related fields from an institute of repute .

3+ years of experience in design verification, with a focus on IP and subsystem verification. Candidates with higher experience will be considered for senior roles.

Proficiency in verification languages and methodologies, such as SystemVerilog, UVM, and other industry-standard tools. Experience with OOPs programming is a plus.

Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.

Experience in AMBA protocols is an advantage.

Excellent problem-solving skills and attention to detail.

Need to have strong oral and written communication skills, with an ability to work as a team player in a fast-paced collaborative environment.

Proven track record of successfully verifying complex IP blocks and subsystems.

Must Have :

Strong background in computer architecture, with experience in verifying either caches, TLB’s , load-store units, on-die memories or coherency verification.