ASIC RTL Design Engineer

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We are hiring Champions in Semicon Industry for exciting career opportunities across various roles

Skill detailed are as below, please take time to go through and do please refer also your friends.

Tech Mahindra Hiring ASIC RTL Engineers for Bengaluru.

Exp : 4-15yrs

Location : Bengaluru

NP : 0-30days

Asic RTL Design, Lint, CDC, Spyglass

JD :

The person would need the ability to elaborate RTL and read in constraints using either Genus or FC to check on syntactical sanity of constraints

Would need a good understanding of RTL clocking structures and develop an understanding of the overall subsystem (which block consumes which clocks and where the timing needs to be met vs. can be ignored)

Understanding of clock grouping concepts, constraints change across DVFS corners

Delivering of constraints at multiple levels of partitioning. Implementation constraints vs. signoff constraints. Porting of constraints from partition level to top level.

Overall understanding and delivery of the functional correctness or the constraints.

Porting over constraints from a third-party IP to constraints.

Kindly share also below details.

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If interested share cv to Ramya.K1@techmahindra.com