We’re Hiring | DFT Engineer / DFT Lead | Bangalore | 4–12 Years
An exciting opportunity to join a global semiconductor design organization working on advanced SoC programs for world-leading customers.
Location : Bangalore (Work From Office)
Experience : 4–20 years
Notice Period : Immediate to 30 Days
Key Responsibilities
- Define and implement SoC-level DFT architecture – Scan, MBIST, LBIST, JTAG / TAP, Compression, Boundary Scan.
- Perform DFT RTL integration, Spyglass checks, Scan insertion, ATPG generation, and pattern debug.
- Collaborate with PD, ATE, and post-silicon teams for test strategy, bring-up, and yield improvement.
- Drive DFT verification and ensure first-pass silicon success.
- Mentor junior team members (for lead roles).
Required Skills
4–12 years of hands-on experience in DFT design and verification.Proficiency in ATPG, MBIST / BISR, JTAG, and Boundary Scan.Experience with tools like Tessent, Spyglass DFT, Synopsys DFTMAX, or equivalent.Strong problem-solving and communication skills.Why Join :
Work on cutting-edge SoC programs, drive innovation, and be part of a growing global semiconductor team delivering first-time-right silicon.
Interested?
Send your profile to Mamatha N – mamatha@gkhrconsulting.com