DFT Architect

Roles and Responsibilities :

• 5+Yrs of experience in DFT Designgee
• Own end-to-end DFT architecture, planning, and implementation for complex SoCs.
• Develop and integrate scan, MBIST / LBIST, boundary scan (IEEE 1149.1 / 1500), and compression.
• Generate ATPG patterns, analyze coverage, and drive defect reduction / yield improvements.
• Expertise with Tessent / DFTAdvisor / SpyGlass-DFT, ATPG, and fault simulation.
• Hands-on with RTL / gate-level insertion, constraints, and timing / area / power trade-offs.
• Silicon bring-up, ATE pattern debug, diagnostics, and failure analysis.
• Strong RTL (Verilog / SystemVerilog), STA basics, scripting (TCL / Python / Perl).
• Collaborate with design / PD / ATE teams;

excellent communicationand documentation.