Design Verification Engineer (Ethernet)

Ethernet Verification : Lead the verification of Ethernet MAC (Media Access Controller) and PHY (Physical Layer) designs, ensuring compliance with Ethernet protocol standards, including 10 / 100 / 1000 Mbps, 1GbE, 10GbE, 100GbE, and others.

Testbench Development : Develop, implement, and maintain scalable and reusable verification environments and testbenches for Ethernet designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.

Protocol Compliance : Ensure that the Ethernet designs conform to Ethernet standards, including the IEEE 802.3 protocol, MAC / PHY interaction, Ethernet framing, packet handling, flow control, and error detection and correction mechanisms.