Job Title
Physical Design Engineer / Senior Physical Design Engineer
Experience : ~4+ years
Location : Bengaluru
Company Overview
Tessolve Semiconductor is a global engineering services company providing end-to-end ASIC / SoC design, test and product engineering solutions. They handle full-chip design through to silicon bring-up across advanced process nodes. Tessolve+3Tessolve+3Tessolve+3
Key Responsibilities
- Work on block-level and / or SoC-level physical design (Place & Route) activities : floor-planning, power planning, placement, clock tree synthesis (CTS), routing, extraction, timing closure, IR-drop / EM, signal integrity, and manufacturability checks (LVS, DRC, Antenna) etc. GrabJobs+1
- Execute full tape-out flows (netlist to GDSII) on advanced process nodes (e.G., 65 / 45 / 40 / 28 / 14 / 10 nm and below) including mixed-signal integration if needed. foundit+1
- Collaborate with cross-functional teams (RTL design, timing / STA, DFT, verification, backend, CAD) to meet power / performance / area (PPA) targets and schedule milestones.
- Mentor and guide junior engineers;
provide technical leadership in the PD domain, as required. jobgrin.Co.In
Drive flow and methodology improvements and automation (scripting in TCL / Perl / Python) for faster, efficient PD closure.Ensure sign-off readiness : timing closure in all process / voltage / temperature corners, power integrity, signal integrity, noise / crosstalk, physical verification (DRC / LVS / Antenna) and manufacturability. Tessolve+1Required Skills & Experience
Bachelor’s or Master’s degree in Electronics, ECE, EE or related discipline.4+ years of relevant physical design (PD) experience in SoC / ASIC / Block-level design flows. GrabJobs+1Hands-on experience in deep-sub-micron process nodes (65 / 45 / 40 / 28 / 14 / 10 nm or below). Familiarity with issues like signal integrity, IR-drop, voltage scaling, routability, manufacturing. foundit+1Strong technical expertise in PD tools and flows : placement, CTS, routing, STA / timing closure, power planning and optimization, physical verification (DRC / LVS), noise / crosstalk, IR / EM analysis. Tessolve+1