Senior DFT Architect

Job Title : Senior DFT Architect

Bangalore, ASIC / SoC Design

We are seeking an experienced technical leader to drive DFT architecture and planning across complex SoC / ASIC designs.

Key Responsibilities :

• DFT Strategy and Architecture : Define and drive DFT strategy and architecture for multiple ASIC / SoC projects.
• Implement DFT Features : Implement and verify DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, IJTAG.
• Manage End-to-End Flow : Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
• Team Collaboration : Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
• Pattern Generation and Debug : Perform pattern generation, fault simulation, and debug test coverage gaps.
• Signoff and Timing Closure : Own DFT signoff, timing closure, and ATE pattern delivery.
• Silicon Bring-Up and Test Vector Validation : Support silicon bring-up, test vector validation on ATE, and yield optimization.
• Mentorship and Automation : Mentor junior DFT engineers, conduct design reviews and training sessions. Develop and maintain DFT automation scripts and infrastructure.

Required Skills and Qualifications :