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Softpath Technologies - DFT Verification Engineer - Embedded System

Softpath Technologies - DFT Verification Engineer - Embedded System

Softpath Technologies LLCBangalore
30+ days ago
Job description

Job Title : DFT Verification Engineer - DDR IP / Subsystem Focus

Experience : 4 - 9 Years

Location : Bangalore (Only Local Candidates Preferred)

About the Role :

We are seeking a talented and motivated DFT (Design for Test) Verification Engineer with solid hands-on experience in DDR IP or Subsystem-level verification. The ideal candidate should have strong expertise in DFT pattern generation and gate-level simulations, particularly targeting DDR interfaces and working with JTAG-based test infrastructure.

You will be responsible for generating silicon test patterns, validating them through simulations, and ensuring robust testability for high-speed DDR interfaces. This role involves close collaboration with RTL designers, DFT architects, and validation engineers to deliver high-quality test solutions for production silicon.

This is a critical engineering position for someone passionate about silicon test strategy, DDR technologies, and pre-silicon verification in advanced SoC designs.

Key Responsibilities :

  • Work as part of the DFT team to verify DDR IP / subsystems using pattern-based testing methodologies.
  • Generate and validate JTAG-based test patterns specifically for DDR interfaces using industry-standard tools and flows.
  • Perform Gate-Level Simulations (GLS) to validate generated test patterns and ensure correct functionality in the post-synthesis / post-layout netlists.
  • Develop verification plans, write testbenches, and debug test pattern failures across RTL and gate-level simulations.
  • Interface with RTL, validation, and test teams to ensure seamless test integration and silicon readiness.
  • Contribute to ATPG / MBIST pattern integration and test coverage improvements for DDR-related logic.
  • Ensure patterns meet structural and functional test goals without impacting design performance.
  • Review timing reports and ensure pattern compliance with design timing requirements.
  • Collaborate closely with DFT architects to enhance test insertion methodologies for high-speed interfaces like DDR.
  • Support lab bring-up / debug of test patterns on silicon (if required).
  • Automate test pattern generation, result analysis, and validation flows using scripting (Tcl, Perl, Python, etc.).

Required Skills and Qualifications :

  • B.E. / B.Tech or M.E. / M.Tech in Electronics, Electrical, or VLSI Design.
  • 4 to 9 years of industry experience in DFT Verification, with specific focus on DDR IP or DDR subsystem-level testing.
  • Strong knowledge of DFT concepts including JTAG, boundary scan, scan insertion, ATPG, and MBIST.
  • Proven experience in pattern generation and gate-level simulation for high-speed interfaces (DDR3 / DDR4 / LPDDR4 / DDR5).
  • Solid understanding of digital logic design, SoC architecture, and memory controller interfaces.
  • Hands-on experience with Verilog / VHDL, SystemVerilog for testbenches, and simulation tools like VCS, NC-Sim, or Questa.
  • Familiarity with DFT tools like TetraMAX, TestMAX, Tessent, or equivalent.
  • Experience in post-synthesis / post-layout simulations, including STA timing reviews and glitch analysis.
  • Proficient in scripting languages : Tcl, Perl, Python, or Shell.
  • Strong debugging skills and ability to root-cause test failures across RTL and GLS domains.
  • Excellent communication and teamwork skills; ability to work independently and within a fast-paced team.

    • Preferred Qualifications :

  • Experience with low-power testing and UPF-based flows.
  • Knowledge of SoC-level DFT integration, including hierarchical scan and clock domain crossings.
  • Familiarity with lab environments and post-silicon validation.
  • Understanding of DDR protocol standards and compliance requirements.

    • Why Join Us?

  • Work on cutting-edge DDR memory subsystem validation in next-gen SoC designs.
  • Be part of an experienced, collaborative, and technically focused team.
  • Opportunity to impact DFT sign-off and first-silicon success of complex chips.
  • Competitive compensation and career advancement opportunities.

    • (ref : hirist.tech)

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