Senior Dft Engineer

Job Description

• Lead complete DFT architecture, planning, and implementation for advanced SoC designs.
• Develop and integrate scan chains, MBIST / LBIST, boundary scan (JTAG IEEE 1149.1 / 1500), and compression logic.
• Generate ATPG patterns, perform coverage analysis, and drive defect reduction and yield improvement.
• Work on RTL / gate-level DFT insertion, constraints handling, timing / area / power trade-offs, and DFT sign-off.
• Perform silicon bring-up, ATE pattern debug, diagnostics, and failure analysis for production readiness.
• Utilize Tessent / DFTAdvisor / SpyGlass-DFT with strong scripting in TCL / Python / Perl for automation and debug.