Key Responsibilities
- Execute full physical design flow for high-performance, low-power GPU cores, including floorplanning, placement & routing (PnR), clock tree synthesis (CTS), power planning, IR drop analysis, signal integrity, and timing closure.
- Perform multi-mode, multi-corner (MMMC) timing analysis and fix violations, implement ECOs, and ensure functional and design-for-test (DFT) constraints are met.
- Collaborate closely with design, DFT, and place-and-route teams to resolve constraint validation, verification, and physical design issues.
- Drive timing convergence and power, performance, and area (PPA) trade-offs in data-path intensive cores.
- Conduct formal and physical verification including DRC / LVS checks and power distribution network (PDN) analysis.
- Develop and maintain automated flows using scripting languages (Perl, Tcl) and shell scripting in Linux / Unix environments.
- Deliver physical design solutions aligned with project milestones while working collaboratively in a multi-engineer team.
Minimum Qualifications
Bachelor's degree or higher in Electrical / Electronics Engineering, Computer Science, or a related field.4+ years of hardware engineering experience for Bachelor's degree holders, or 3+ years for Master's degree holders, or 2+ years for PhDs.Strong expertise with industry-standard physical design tools such as Synopsys ICC2, Cadence Innovus, PTSI, and Tempus in advanced technology nodes.Proven experience in physical implementation of high-performance GPU or similar complex cores, including timing closure and power optimization.Deep understanding of clocking architectures and advanced static timing analysis (STA).Proficiency in scripting languages (Perl, Tcl) and Linux / Unix shell scripting.Demonstrated ability to work effectively in team environments under project deadlines.Excellent problem-solving and communication skills.Preferred Qualifications
8+ years of experience in physical design / implementation.Prior experience working on GPU or high-speed digital cores.Hands-on experience with formal verification and physical verification flows.Skills Required
hardware engineering , Fpga, Physical Design, Computer Science, Design Engineering, Gpu