RTL Design Engineer Lead & Design Verification

This will be a general RTL Design & DV requirement for SoC Level.

Ability to write RTL code for a given Design's microarchitecture independently.

RTL Integration of IPs / Subsystems to an SoC

RTL quality checks for sign off ( Lint. CDC. Equivalence Checks, Static Power checks)

Ability to build Test Benches independently in UVM ( Strong in SV, UVM, Assertions, some protocol knowledge) - Test Component Development, Test Case development, Coverage closure, Regression maintenance and debug