RTL design Engineer

General Summary :

• Experience in Logic design / micro-architecture / RTL coding is a must.
• Must have hands on experience with SoC design and integration for complex SoCs.
• Experience in Verilog / System-Verilog is a must.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking / reset / debug architecture and peripherals like USB, PCIE and SDCC.
• Understanding of Memory controller designs and microprocessors is an added advantage
• Hands on experience in constraint development and timing closure
• Work closely with the SoC verification and validation teams for pre / post Silicon debug
• Hands on experience in Low power SoC design is required
• Experience in Synthesis / Understanding of timing concepts for ASIC is required.
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Experience creating pad ring and working with the chip level floorplan team is an added advantage
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required .

Minimum Qualifications :

Preferred Qualifications

Skills Required

SOC design, Electrical Engineering, Verilog, Axi, cdc, Rtl Design, AHB