IP Verification Lead

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SMTS SILICON DESIGN ENGINEER - Verification Lead

The Role

As an SMTS Design Verification Engineer in AMD's Infinity (Data) Fabric team, you will be a senior technical leader responsible for driving verification of high-performance, scalable fabric IP that connects compute, memory, and I / O subsystems across AMD's CPUs, GPUs, and APUs. You will lead verification strategy, ensure methodology excellence, and mentor other engineers while collaborating with architects and designers to deliver world-class silicon.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

Key Responsiblities

• Own verification strategy and execution for complex Data Fabric IP blocks and subsystems from spec review through tape-out.
• Define and architect UVM-based testbench infrastructure for scalability, reusability, and high coverage across product generations.
• Lead test plan creation and sign-off, integrating both constrained-random and directed testing methodologies.
• Drive coverage-driven verification — define, track, and close both functional and code coverage goals.
• Collaborate cross-functionally with design, architecture, and performance teams to debug complex issues and ensure first-pass silicon success.
• Mentor and guide junior and mid-level verification engineers, reviewing their code, test plans, and coverage results
• Identify and drive verification methodology improvements, automation, and process optimizations to enhance team productivity.
• Participate in post-silicon debug and validation, assisting in recreating and root-causing issues found in lab or customer systems

Preferred Experience

Academic Credentials

Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Skills Required

Perl, Uvm, systemverilog, Python