Principal RTL Design Engineer

Staff / Principal RTL Design Engineer : -

Bangalore

Founded in 2023,by Industry veterans HQ in California,US

Location : Greater Bengaluru Area

Company Description :

We are product based startup. The products are chipsets and intelligent machines that enable scalable enterprises AI, streaming video intelligence, training trillion parameter models, and fine-tuning LLMs, allowing enterprises to improve productivity with advanced solutions. We are looking for exceptional talent and leadership to join our organization, the world’s first company developing Agentic Silicon for powering the future of AI.

We are pioneering a new era in AI innovation focused on accelerating the

adoption of end-to-end enterprise AI, from the edge to Zettascale systems.

Our cutting-edge Software and composable silicon Chiplets will transform the way AI models are Trained, Deployed, and Scaled.

"Join Our Growing Team!"

We are building a world-class team to drive innovation in AI Silicon & Software and hiring for below position in Bangalore.

Job Description :

As a member of Design(RTL) team, you will be responsible for the micro-architecture and design of IPs / Controllers for SoC / SiP designs.

o Perform architectural / design trade-offs for required product features,

performance and system constraints.

o Responsible for defining and documenting design specifications.

o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements.

o Design and Implement logic functions that enable efficient test and debug.

o Provide Debug support for design verification and post-silicon activities.

Skill and Experience Requirements :

o Minimum 5-15 + years industry experience with Master’s degree (preferred) or Bachelors degree in Electrical or Computer Engineering.

o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86 / ARM CPU Processors or high-speed custom ASICs / Accelerators

with focus on any one : Cache controller, IO interfaces (PCIe, CXL, Ethernet),

Fabric / Interconnects / Noc / D2D

UCIe, Memory controllers, Display, Video encoding / transcoding.

o Good understanding of ASIC design flow including RTL design, verification, logic

synthesis and timing analysis and sign-off quality flows.

• o Self-starter with strong interpersonal and communication skills .

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"