Principal RTL Design Engineer / Co-founder - AI / ML Accelerator

Job description

• Lead / Own a world class NPU for Edge AI Inference
• Develop ultra-low-power machine learning chips for intelligent sensing and autonomous navigation
• Architect / Work independently and collaboratively to create and review ASIC / SoC subsystem design architecture and micro architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC / SoC products according to established coding and quality guidelines.
• Work with Design Validation (DV) teams to create test plans for, verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Key qualifications

P.S. This is for someone who is mature enough with urge to do his / her startup and able to sustain with equity only (till we get external funding)