Rtl Design Lead

Job Title : RTL Design Engineer (Mid–Senior Level)

Location : [BLR / HYD]

Experience : 7– 15 years

Employment Type : Full-time

Department : Digital Design / SoC Engineering

Position Overview

We are seeking a highly skilled RTL Design Engineer with strong experience in digital design, architecture bring-up, RTL integration at SoC level, and RTL quality sign-off. The ideal candidate will work closely with architects, verification, physical design, and validation teams to ensure high-quality RTL delivery across multiple IP and SoC programs.

Key Responsibilities

Architecture & Design Bring-Up

Collaborate with system and architecture teams to understand high-level specifications and convert them into micro-architecture and RTL design.

Contribute to the development and review of block-level and top-level architecture documents.

Drive design partitioning, clock / reset / power domain planning, and interface definition.

RTL Design & Integration

Develop synthesizable RTL in Verilog or System Verilog for SoC subsystems and IP blocks.

Perform RTL integration at subsystem and SoC level, ensuring clean connectivity, interface alignment, and proper clock / reset integration.

Own end-to-end RTL integration flow, including configuration management, build, and sanity checks.

RTL Quality Checks & Sign-off

Run and close lint, CDC / RDC, synthesis, DFT, and other static checks to ensure design readiness.

Manage formal checks, low-power (UPF / CPF) validation, and simulation bring-up as part of the sign-off process.

Ensure RTL meets quality, performance, and timing closure requirements before release to downstream teams.

Cross-functional Collaboration

Work closely with Verification, Physical Design, and Firmware teams for seamless design handoff.

Participate in design reviews, code walkthroughs, and cross-domain debug activities.

Support post-silicon validation by helping analyze functional or timing-related issues.

Release Management

Own RTL freeze and release management to different stakeholders (DV, PD, Validation).

Maintain version control, design documentation, and configuration traceability across project milestones.

Required Skills & Experience

Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering.

5–12 years of hands-on experience in RTL design and SoC integration.

Strong expertise in Verilog / SystemVerilog, SoC architecture, and digital logic design fundamentals.

Hands-on experience with tools like :

Lint (SpyGlass, Ascent Lint, etc.)

CDC / RDC (SpyGlass, Questa CDC, etc.)

Synthesis (Design Compiler, Genus, etc.)

Formal verification and low-power (UPF / CPF) checks.

Familiarity with configuration management tools (Git, Perforce, or similar).

Understanding of timing closure concepts, DFT, and simulation environments.

Excellent analytical, debugging, and communication skills.

Good to Have

Exposure to high-performance or low-power SoC architectures.

Experience with AXI / AHB / ACE / CHI or other standard bus protocols.

Familiarity with Emulation / FPGA prototyping and post-silicon bring-up.

Knowledge of EDA automation (TCL, Python, or Make).

Please share your jhansi.bv@leadsoc.com for further discussion