ASIC Physical Design, Staff Engineer

What You ll Be Doing :

• He / She will be part of SNPS DDR / HBM / Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes.
• Timing closure above 4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
• Prior working knowledge in the DDR / HBM / HBI timing closure, implementation would be an added advantage.
• Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality.

Who You Are :

Skills Required

DDR / HBM / UCIe IP implementation, High-speed timing closure (~4GHz), Mixed-signal hard macro integration, Clock tree synthesis (CTS)