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R&D Engineering, Staff Engineer - IP Verification

ConfidentialBengaluru / Bangalore

30+ days ago

Job description

Expertise in UVM and System Verilog

Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage.

Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM / OVM / UVM methodologies.

Protocol experience : Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol

Skills Required

Uvm, systemverilog, Usb

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Verification Engineer • Bengaluru / Bangalore