RTL Design Engineer | FINJO I988

Experience Required : Minimum 8 years.

Project experience with ARM-based ecosystem components

M7, Coresight, NIC, and other AMBA bus interconnects

Familiarity with AMBA bus protocols and SoC system debug infrastructure

Strong experience with micro-architecture, Verilog / System Verilog, Synthesis, timing constraints development, Lint , CDC checks

Understanding of SoC interfaces like QSPI, UART, GPIand Os

Capable of working with multiple IP vendors and other IP teams

Plus points : experience with HBM DRAM memory controllers and their interfaces, Plus points : experience with UCIe

Time zone : US US-based preferred / Remote work