Senior Design Verification Engineer

JD :

This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies.

Key Responsibilities :

Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies.

Design and implement verification environments using SystemVerilog and UVM methodologies.

Develop test cases to validate functional correctness, performance, and compliance with industry standards.

Collaborate with the design team to debug and resolve issues identified during verification.

Perform coverage analysis to ensure thorough verification of the design.

Required Skills :

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

Experience in ASIC / FPGA verification with a focus on PCIe, Ethernet, CXL, DDR, and RISC-V protocols.

Proficiency in SystemVerilog and familiarity with UVM methodology.

Strong problem-solving and debugging skills.

Excellent communication and teamwork abilities.

Preferred Skills :

Familiarity with high-speed serial interfaces such as PCIe Gen4 / Gen5, Ethernet 400G / 800G, or CXL.

Experience with verification tools such as VCS, Questa, or ModelSim.

Knowledge of scripting languages such as Perl or Python.

Understanding of computer architecture and digital logic design principles.