Senior Design Verification Engineer

Job Summary :

We are seeking a highly skilled Verification Engineer with extensive experience in SystemVerilog and UVM methodologies. The ideal candidate will have a strong background in SoC-level verification, debugging firmware and RTL, and developing automated verification workflows in complex compute environments.

Key Responsibilities :

• Perform SoC-level verification using SystemVerilog and UVM methodologies.
• Develop and enhance UVM-based verification frameworks, testbenches, and processes.
• Debug firmware and RTL code using industry-standard simulation tools.
• Automate verification workflows in distributed compute environments to improve efficiency.
• Collaborate with cross-functional teams to ensure design quality and performance.
• Work on simulation profiling, performance optimization, and acceleration activities.
• Contribute to HLS (High-Level Synthesis) tool and process improvements.
• Ensure high verification coverage and maintain comprehensive documentation.

Required Skills & Experience :

Preferred Qualifications :

Skills Required

C, Linux, Perl, Verilog, Uvm, Windows, systemverilog, Python