AMS Verification Engineer
Experience : 3 to 5 Years
Location : Bangalore
Job Description
Perform Analog Mixed-Signal (AMS) verification using
SystemVerilog, Wreal, and Verilog-AMS
for IP and subsystem-level designs.
Develop and maintain
mixed-signal testbenches
, behavioral and
real-number models (RNM)
for analog / digital interfaces.
Drive
functional and regression verification
, ensuring coverage closure and model-to-SPICE correlation.
Collaborate closely with analog and digital design teams to debug AMS integration and simulation issues.
Hands-on experience with
Cadence AMS Designer, Xcelium, Spectre
, or
Synopsys VCS AMS
Good understanding of analog concepts such as
PLLs, ADC / DACs, SerDes, or Power Management IPs
Scripting skills in
Python, Perl, or TCL
for automation and flow enhancements are preferred.
Verification • India