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Staff Engineer, R&D
ConfidentialBengaluru / Bangalore30+ days ago
Job descriptionRequirements : Bachelors / masters with good academic record. 5+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM / OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a work exposure on any of the industry standard protocols like Jedec UFS, MIPI Unipro, MIPI MPHY, PCIe, USB, Ethernet, etc. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. Leadership qualities to motivate and align team members towards business goals and priorities. As a motivator / leader of the R&D team in Synopsys, you will be responsible for Development and enhancements of features, flows and solutions Quality execution of VIP development, taking responsibility for designing, developing, debugging, creation of reliable plans and effort estimates for your projects. Focus on innovation to ensure continuous product enhancements
Skills Required
systemverilog, Usb, Ethernet
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Staff Engineer • Bengaluru / Bangalore
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