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Principal Verification Design Engineer
Principal Verification Design EngineerCadence System Design and Analysis • indore, India
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Principal Verification Design Engineer

Principal Verification Design Engineer

Cadence System Design and Analysis • indore, India
17 hours ago
Job description
  • BE / BTech / ME / MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • 5+ years of Design Verification experience with SV / UVM
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

    • Prior experience in IP verification of memory IP (DDR / HBM / GDDR) would be an added advantage.

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    Design Verification Engineer • indore, India

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