Design Verification Engineer - RTL

Job requirements - Technical Skills :

• Complete hands-on experience in RTL Verification at both SoC / IP level.
• Should be proficient in building New or maintain existing SV / UVM / C based testbenches.
• Experienced in SV-UVM / OVM / VMM Methodologies. Specman hands-on can be a plus.
• Should have handled Complex Blocks / Hard Macro Level Functional Verification at both RTL and Gate Level.
• Should have experience dealing with Coverage Models and metrics issue and closure based on specification.
• Able to develop and track Test Plan & Validation Plans based on Specification. Able to setup Regression environments based on Test Plans.
• Experience in dealing GPIO, Clock Controller, DFTMUX, System controller such as PMU / CMU / TMU and power issues at SoC level will be an advantage.
• Knowledge on Power-Aware -CPF / UPF Simulation at both RTL and Timing Simulations at Gate Level.
• Able to Work closely with the Architecture, Design, Synthesis and Physical Design team teams to resolve the RTL / GLS level issues.
• Should have knowledge on any of the Bus interface - Should have worked on AMBS protocols.

Technologies : 28nm and below.

Education :

Job requirements - Soft Skills :

Communication :

Highlight potential issues :

(ref : hirist.tech)