Expert DFT Leadership Opportunity for High-Performance SoCs and ASICs
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We are seeking an experienced leader to drive DFT architecture, planning, and implementation across complex SoC / ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
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Main Responsibilities :
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- Define and drive DFT strategy and architecture for multiple ASIC / SoC projects.
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Implement and verify DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, IJTAG.">
Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.">
Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.">
Perform pattern generation, fault simulation, and debug test coverage gaps.">
Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.">
Support silicon bring-up, test vector validation on ATE, and yield optimization.">
Mentor and guide junior DFT engineers; conduct design reviews and training sessions.">
Develop and maintain DFT automation scripts and infrastructure.">
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Requirements : ">
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Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.">
7+ years of experience in DFT for complex ASIC or SoC designs.">
Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.">
Hands-on experience with DFT tools such as Synopsys, Siemens EDA, Cadence / others.">
Strong knowledge of RTL design, STA, and synthesis flows.">
Proficient in scripting languages (Python, Perl, Tcl) for flow automation.">
Deep understanding of silicon test challenges and test coverage improvement.">
Strong leadership, team collaboration, and communication skills.">
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What We Offer : ">
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Lead DFT for high-performance, next-gen SoCs and ASICs.">
Collaborate with top-tier engineers and global semiconductor leaders.">
Fast-track growth opportunities.">
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