Job Title : RTL Design Lead – SoC Integration (HBM / PCIe Gen6)
Experience Required : 8+ Years
Employment Type : Full-Time
Preferred Notice Period : Immediate Joiner
Locations : Bangalore, Hyderabad, Chennai, Pune, Noida, Ahmedabad, Indore
Job Description
We are seeking an experienced RTL Design Lead with strong expertise in SoC Integration , specifically involving HBM (HBM3 / 3E) and / or PCIe Gen6 . The ideal candidate will be responsible for leading RTL design, driving complex IP integration, and ensuring high-quality deliverables across the SoC development lifecycle.
Key Responsibilities
- Lead RTL design, micro-architecture, and integration activities for high-performance SoC components.
- Own integration of HBM subsystems and / or PCIe Gen6 controllers.
- Collaborate with Architecture, Verification, PD, and DFT teams to ensure optimal design closure.
- Perform timing-aware RTL development, lint, CDC / RDC analysis, and debug complex SoC-level issues.
- Conduct design reviews, ensure compliance to design quality standards, and mentor junior engineers.
Required Skills & Experience
Minimum 8 years of experience in RTL design and SoC integration.Hands-on expertise with HBM (HBM3 / 3E) and / or PCIe Gen6 integration.Strong proficiency in SystemVerilog , AMBA protocols, synthesis flows, STA constraints, and CDC / lint methodologies.Experience debugging complex SoC architectures and driving technical ownership.Strong communication and leadership abilities.Good to Have
Exposure to chip bring-up or post-silicon activities.Experience with low-power design techniques.Prior mentoring or team lead responsibilities.