Job Description – Senior Synthesis Engineer (VLSI)
Position Overview
We are seeking a highly motivated and experienced Senior Synthesis Engineer with a strong background in VLSI design. The ideal candidate will have hands-on expertise in advanced technology nodes, physical synthesis, low-power methodologies, and cross-functional collaboration to meet aggressive PPA targets.
Key Responsibilities
- Perform RTL-to-Gate Synthesis and Physical Synthesis across multiple corners and modes (MCMM) using industry-standard tools such as Fusion Compiler or Genus .
- Drive timing closure , power optimization , and area reduction to achieve design PPA goals.
- Conduct Logic Equivalence Check (LEC) and low-power structural checks using tools like Conformal LEC or Formality , and debug issues to ensure clean signoff.
- Perform pre-STA timing analysis using PrimeTime or Tempus .
- Run and analyze low-power verification checks using Conformal Low Power (CLP) or VCLP .
- Verify constraints quality and completeness and ensure design compliance with spec.
- Work with UPF and low-power design concepts throughout the synthesis and signoff process.
- Support functional ECO flows and implement ECO changes with minimal impact on PPA.
- Collaborate with RTL, DFT, and Physical Design teams to debug issues and ensure smooth handoff.
- Provide input and debugging support for DFT insertion and basic DFT-related challenges.
- Develop and maintain automation using TCL / Perl / Shell scripting to enhance productivity and design quality.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field.Minimum 3 + years of experience in Synthesis and Physical Synthesis.Hands-on experience with advanced technology nodes ( 7nm, 5nm, or below ).Strong understanding of low power design , UPF , and multi-mode / multi-corner analysis.Proven debugging, analytical, and problem-solving skills.Self-driven with strong initiative, ownership, and the ability to work in fast-paced environments.