Job Description
Experience in all phases of the IC design process from RTL->
GDS2
Physical implementation of SoC / Full-chip-level and / or high-speed CPU / GPU / DSP cores
Experience in high-speed, low-power, mixed-signal SoC’s is a plus
Experience in developing PNR methodology / flow to and supporting a larger PD team
Experience on floor planning, clocking & power network architecture and design
Experience in low-power implementation using UPF / CPF power intent flow
Experience in I / O Ring, RDL routing, bumps and other top-level design considerations
Experience in LVS / DRC / ERC, EMIR (static & dynamic), LEC and Reliability sign-off checks
Experience in STA analysis, timing closure and defining chip sign-off criterion
Thorough understanding of digital design, timing analysis, and DFT
Good understanding of foundation IP components – Standard cells, SRAMs etc.
EDA Tools : Synopsys (DCT, ICC2, PT-SI, Red hawk), Cadence (Genus, Tempus, Innovus, Voltus)
Requirements
Qualifications :
BTech / MTech / PhD with 4-6years’ experience in physical implementation.
Proven track record with multiple successful final production tape-outs.
Proven ability to independently deliver results in a very fast-moving startup environment, be able to work hands-on as and guide / help peers to deliver their tasks.
Be able to work under limited supervision and take complete accountability.
Excellent written and verbal communication skills.
Benefits
What’s in it for you :
Work on leading edge technologies
An opportunity for career development and growth
Competitive compensation
Exceptional benefits
Company : Eteros Technologies India Private Limited
Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Hyderabad and Ahmedabad
Lead Design Engineer • Hyderabad, Telangana, India