Senior physical design engineer

Company Overview :

We are Mos Chip – A trusted technology partner for SILICON | PRODUCT | AI / ML Engineering. With 1400+ engineers and domain experts across India and the USA, Mos Chip continues to bring in digital and product transformation for businesses across industries. We offer engineering solutions comprising of systems and product design, Io T solution design, artificial intelligence and Machine Learning, FPGA design, Mixed Signal IP design, ASIC design, verification, and validation.

Mos Chip is a publicly traded company headquartered in Hyderabad, India, with a vision to be a preferred partner for technology and excellence throughout the entire product / solution development cycle, designing comprehensive and best-in-class solutions on time to achieve business and operational goals. Our team of experts empowers businesses, technology providers, and manufacturers to deliver innovative, customized, and scalable solutions for domains like Automotive, Media & Entertainment, Industrial and Home Automation, Consumer Electronics, Telecommunications, Computer Vision, Networking, Data Center, Healthcare, etc

Job Description :

Experience : 4 - 12 Years

Location : Hyderabad ( Work From Office)

Required skills :

He / She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis / closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He / She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.

• Provide technical guidance, mentoring to physical design engrs.
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
• Timing closure on DDR2 / DDR3 / PCIE interfaces.
• Excellent communication skills.
• Strong Back ground of ASIC Physical Design : Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.