Senior / Principal Asic Rtl Design Engineer (Soc / Subsystem)

My name is Shahid I am reaching out with a role that fits engineers who enjoy real ownership, from shaping micro-architecture to watching their RTL come alive in silicon. If you’re looking for a space where your design decisions actually matter, this one is worth your time.

Job Title - Senior / Principal ASIC RTL Design Engineer (SoC / Subsystem)

Location -Bangalore, Karnataka

Job Description :

Job Summary : Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.

Responsibilities :

• Define micro-architecture from specs;

write high-quality synthesizable SystemVerilog / Verilog RTL for SoC-level or large subsystems.

support emulation / FPGA only as a secondary validation aid (not counted toward the 8 years).

Nice to have :

Best,

Shahid