Senior / Lead STA engineer

We’re Hiring : STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad

Company : ACL Digital Company

Location : Bangalore & Hyderabad

Experience : 5 to 15 Years

Job Type : Full-Time

ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.

If you’re an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you!

Responsibilities :

• Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes
• Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.)
• Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations
• Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure
• Contribute to methodology improvements and timing signoff strategies
• Report timing status, risks, and closure plans to technical leads and project stakeholders

Required Skills & Experience :

Why Join Wafer Space?

Interested?

Send your resume to vaishnavi.suvarna@acldigital.com