Design Engineer 2

Job Description :

Tessolve is looking for an experienced Physical Design Engineer to join our team in Bangalore. The ideal candidate will have a strong background in RTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools for floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.

Key Responsibilities :

• End-to-end physical design flow from RTL to GDSII at advanced technology nodes (7nm, 5nm, or below).
• Floorplanning and Partitioning : Optimize chip area, power, and performance.
• Placement and CTS : Optimize standard cell placement, buffer insertion, and clock tree synthesis.
• Routing and Timing Closure : Work on congestion analysis, RC extraction, and static timing analysis (STA).
• Power Optimization : Implement low-power techniques such as clock gating, power gating, and multi-voltage domains.
• Physical Verification : Perform DRC, LVS, and Antenna checks using industry-standard tools.
• Sign-off Analysis : Work on IR drop, Electromigration (EM), and Signal Integrity (SI) analysis.
• Collaborate with RTL design, DFT, and verification teams for design convergence.
• Debug and resolve timing, power, and physical verification issues.

Required Skills :

Preferred Qualifications :

Why Join Tessolve

If you are passionate about Physical Design and looking for an exciting opportunity at Tessolve, apply now!

Skills Required

EDA Tools, Static Timing Analysis