Job Title : Design Verification Engineer – SoC / IP / Subsystem
Locations : Bangalore | Hyderabad | Pune | Chennai
Email : prabhu.p@acldigital.com
WhatsApp : +91 87543 87484
About the Role
ACL Digital is expanding its Semiconductor Design Verification team! We’re hiring Design Verification Engineers with expertise across SoC, IP, and Subsystem levels to work on leading-edge semiconductor projects for global technology customers.
If you have experience with protocol-level verification, ARM-based designs, and power-aware or mixed-signal verification, we’d love to connect with you!
Experience Range : 4 to 20+ years
(We have multiple positions open across SoC, IP, and Subsystem verification levels.)
Key Responsibilities
Technical Skills Required
✅ Strong expertise in SystemVerilog & UVM methodology
✅ Hands-on experience with C, Verilog, and scripting (Python / Perl / Tcl)
✅ Experience in one or more protocols : PCIe / Ethernet / USB / MIPI / DDR / Wi-Fi / Bluetooth
✅ ARM Ecosystem : Coresight / Cortex / Subsystem verification
✅ Low Power & Power-Aware Verification : UPF / CPF, Low-Power GLS
✅ Mixed-Signal Verification : AMS Co-simulation exposure preferred
✅ Familiarity with tools such as VCS, Xcelium, Questa, Verdi, DVE, JasperGold
Qualifications
B.E / B.Tech / M.E / M.Tech in Electronics, ECE, or related disciplines
Strong analytical, debug, and problem-solving skills
⚙️ Exposure to verification methodologies at IP, Subsystem, or SoC levels
Why Join ACL Digital?
Work on next-generation SoC / IP / Subsystem verification projects with top global semiconductor clients
Exposure to AI, Automotive, 5G, Networking, and IoT domains
Flexible locations : Bangalore | Hyderabad | Pune | Chennai
Collaborative environment with strong focus on technical excellence & career growth
Interested? Apply Now!
Send your resume to prabhu.p@acldigital.com or WhatsApp +91 87543 87484
Learn more : https : / / www.acldigital.com / industries / semiconductor
Design Verification Engineer • India