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ACL DigitalIndia14 days ago
Job description
DV Engineer
Experience : 1-3 years
Location : Hyderabad
- Verilog, System verilog, UVM
- VHDL, UVVM
- 3rd party simulator exposure with VCS, Questa, Xcelium
- Proficient in simulation and HW languages
- Should be able to interpret various LRMs and comply with semantics and testcase creation.
Interested,please drop your updated resume to janagaradha.n@acldigital.com
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Design Verification Engineer • India
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