PDK / CAD Engineer, Sr Lead - Physical Verification Development

Job Area :  Engineering Group, Engineering Group >

Hardware Engineering

General Summary : Job Overview

In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state of the art tools. You will be collaborating with the Custom Digital / Analog / Mixed Signal / RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and / or modify the existing ones

Minimum Qualifications :

Bachelor's degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Minimum Qualification

Minimum 5 years experience in a hands-on PDK role

Expertise in Calibre / ICV runset coding for DRC / LVS / ERC / PERC / ESD / Latch-up / Antenna'.

As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology

Code custom checks such as Layout / Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules(DRCs), etc to meet the needs of the design teams

You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and / or modify existing ones.

Proficiency in integration and tech setup of Calibre LVS with StarRC / QRC and other Extraction tools

Support the design teams with solving their PV challenges to facilitate the IP release and Chip tapeouts

Collaborate with tool vendor and foundries for tools and flow improvements

Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design

Proficiency in one or more of the programming / scripting languages- , Python, Unix, Perl, and TCL.

Good communication skills and ability to work collaboratively in a team environment

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If you would like more information about this role, please contact Qualcomm Careers.

Skills Required

Sta, Floor Planning, Timing Closure, LVS, Scripting Languages, Physical Design