Physical Design Manager

The Role We are seeking an experienced Physical Design Manager to lead SoC / IP implementation on advanced nodes (7nm and below). The role requires strong technical expertise, leadership, and ownership of execution from RTL to GDSII for first-pass silicon success. Key Responsibilities

• Lead end-to-end Physical Design flow (RTL-to-GDSII) for SoCs / IPs.
• Own floorplanning, placement, CTS, routing, STA, IR / EM, and signoff.
• Drive PPA optimisation, ECO closure, and physical verification.
• Collaborate with RTL, verification, architecture, and packaging teams.
• Lead EDA flow automation and scripting for efficiency.
• Mentor and manage a high-performing physical design team. Key Skills & Experience

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