VLSI RTL Design Lead
HCLTechthane, India19 hours ago
Job descriptionBachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 10+ years of proven experience in RTL design for complex ASICs or SoCs Extensive knowledge of digital design principles and advanced concepts (pipelining, clock gating, low-power design) Demonstrated ability to lead and mentor junior engineers, fostering a positive team environment Expertise in Verilog and VHDL with a strong grasp of coding styles, optimization techniques, and reusability principles In-depth experience with verification methodologies (UVM, formal verification) and verification tools Experience with synthesis tools, SDC format, and advanced timing closure techniques Excellent problem-solving skills, a meticulous eye for detail, and a proactive approach Strong communication, collaboration, and leadership skills to effectively lead and guide the team Competitive salary and benefits package commensurate with experience Opportunity to lead and influence on high-impact projects Collaborative and stimulating work environment with intellectual challenges Potential for professional development and advancement into leadership roles
Job Summary :
Are you a seasoned RTL Design Engineer with a passion for pushing the boundaries of digital design? We are looking for a highly experienced and motivated individual to join our team and lead the development of complex RTL for cutting-edge ASICs and SoCs. In this senior role, you will leverage your expertise to tackle challenging projects, mentor junior engineers, and contribute significantly to our hardware development process.
Responsibilities :
- Lead the design and implementation of complex digital logic blocks and subsystems using Verilog or VHDL
- Architect and define micro-architectures for high-performance and area-optimized designs
- Champion best practices in RTL coding, ensuring code maintainability, readability, and adherence to coding standards
- Develop and implement comprehensive verification plans using advanced methodologies (e.g., UVM, formal verification)
- Perform in-depth static timing analysis (STA) and actively participate in achieving timing closure
- Integrate and interface designed modules with other subsystems, ensuring seamless functionality
- Mentor and guide junior engineers, fostering a collaborative and knowledge-sharing environment
- Stay abreast of the latest advancements in RTL design tools, methodologies, and industry trends
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